Jan. Die PCIe Slots haben aber einen 2er Abstand Klar, ich könnte jetzt ne 2-Slot Bridge bestellen. Allerdings sollen laut Mainboard Handbuch. Jan. Kostengünstig soll der neue PCI-Express-Slot sein. Deshalb schrumpfen .. Abstand der einzelnen Pins beträgt 0,8 mm. Das Interface liefert. Sept. mal eine Frage, ist der Abstand zwischen dem Sockel und dem ersten PCIe Slot bei einem Intel ATX Board eigentlich genormt? (blaue Linie).
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However, there are cards either on or coming on to the market that will make use of the pcie x1 slot.
Currently Network cards and SATA cards seem to be the main thing it's used for, and i believe Matrox does make a video card on PCIE 1x, it's not exactly a gamer's card though 32 meg vram.
The x1 actually refers to the data transfer speed of the PCIe x1 slot. It has nothing to do with the number of PCIe slots. Scroll down to PCI Express slots: You must log in or sign up to reply here.
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Your name or email address: Do you already have an account? The PCI standard permits multiple independent PCI buses to be connected by bus bridges that will forward operations on one bus to another when required.
Although conventional PCI tends not to use many bus bridges, PCI express systems use many; each PCI express slot appears to be a separate bus, connected by a bridge to the others.
Generally, when a bus bridge sees a transaction on one bus that must be forwarded to the other, the original transaction must wait until the forwarded transaction completes before a result is ready.
One notable exception occurs in the case of memory writes. Here, the bridge may record the write data internally if it has room and signal completion of the write before the forwarded write has completed.
Or, indeed, before it has begun. Such "sent but not yet arrived" writes are referred to as "posted writes", by analogy with a postal mail message. Although they offer great opportunity for performance gains, the rules governing what is permissible are somewhat intricate.
The PCI standard permits bus bridges to convert multiple bus transactions into one larger transaction under certain situations.
This can improve the efficiency of the PCI bus. There are two additional arbitration signals REQ and GNT which are used to obtain permission to initiate a transaction.
All are active-low , meaning that the active or asserted state is a low voltage. Pull-up resistors on the motherboard ensure they will remain high inactive or deasserted if not driven by any device, but the PCI bus does not depend on the resistors to change the signal level; all devices drive the signals high for one cycle before ceasing to drive the signals.
All PCI bus signals are sampled on the rising edge of the clock. Signals nominally change on the falling edge of the clock, giving each PCI device approximately one half a clock cycle to decide how to respond to the signals it observed on the rising edge, and one half a clock cycle to transmit its response to the other device.
The PCI bus requires that every time the device driving a PCI bus signal changes, one turnaround cycle must elapse between the time the one device stops driving the signal and the other device starts.
Without this, there might be a period when both devices were driving the signal, which would interfere with bus operation. The combination of this turnaround cycle and the requirement to drive a control line high for one cycle before ceasing to drive it means that each of the main control lines must be high for a minimum of two cycles when changing owners.
The PCI bus protocol is designed so this is rarely a limitation; only in a few special cases notably fast back-to-back transactions is it necessary to insert additional delay to meet this requirement.
Any device on a PCI bus that is capable of acting as a bus master may initiate a transaction with any other device.
To ensure that only one transaction is initiated at a time, each master must first wait for a bus grant signal, GNT , from an arbiter located on the motherboard.
Each device has a separate request line REQ that requests the bus, but the arbiter may "park" the bus grant signal at any device if there are no current requests.
The arbiter may remove GNT at any time. The arbiter may also provide GNT at any time, including during another master's transaction. A device may initiate a transaction at any time that GNT is asserted and the bus is idle.
A PCI bus transaction begins with an address phase. Actually, the time to respond is 2. Note that a device must latch the address on the first cycle; the initiator is required to remove the address and command from the bus on the following cycle, even before receiving a DEVSEL response.
The additional time is available only for interpreting the address and command after it is captured. On the fifth cycle of the address phase or earlier if all other devices have medium DEVSEL or faster , a catch-all "subtractive decoding" is allowed for some address ranges.
On the sixth cycle, if there has been no response, the initiator may abort the transaction by deasserting FRAME. PCI devices therefore are generally designed to avoid using the all-ones value in important status registers, so that such an error can be easily detected by software.
Targets latch the address and begin decoding it. Subtractive decode devices, seeing no other response by clock 4, may respond on clock 5.
If the master does not see a response by clock 5, it will terminate the transaction and remove FRAME on clock 6. The initiator may assert IRDY as soon as it is ready to transfer data, which could theoretically be as soon as clock 2.
To allow bit addressing, a master will present the address over two consecutive cycles. On the following cycle, it sends the high-order address bits and the actual command.
Dual-address cycles are forbidden if the high-order address bits are zero, so devices which do not support bit addressing can simply not respond to dual cycle commands.
Addresses for PCI configuration space access are decoded specially. For these, the low-order address lines specify the offset of the desired PCI configuration register, and the high-order address lines are ignored.
Each slot connects a different high-order address line to the IDSEL pin, and is selected using one-hot encoding on the upper address lines.
After the address phase specifically, beginning with the cycle that DEVSEL goes low comes a burst of one or more data phases.
In case of a write, the asserted signals indicate which of the four bytes on the AD bus are to be written to the addressed location. In the case of a read, they indicate which bytes the initiator is interested in.
For reads, it is always legal to ignore the byte enable signals and simply return all 32 bits; cacheable memory resources are required to always return 32 valid bits.
The data phase continues until both parties are ready to complete the transfer and continue to the next data phase. Whichever side is providing the data must drive it on the AD bus before asserting its ready signal.
Once one of the participants asserts its ready signal, it may not become un-ready or otherwise alter its control signals until the end of the data phase.
The data recipient must latch the AD bus each cycle until it sees both IRDY and TRDY asserted, which marks the end of the current data phase and indicates that the just-latched data is the word to be transferred.
This continues the address cycle illustrated above, assuming a single address cycle with medium DEVSEL, so the target responds in time for clock 3.
However, at that time, neither side is ready to transfer data. For clock 4, the initiator is ready, but the target is not.
On clock 5, both are ready, and a data transfer takes place as indicated by the vertical lines.
For clock 6, the target is ready to transfer, but the initiator is not. On clock 7, the initiator becomes ready, and data is transferred.
For clocks 8 and 9, both sides remain ready to transfer data, and data is transferred at the maximum possible rate 32 bits per clock cycle.
In case of a read, clock 2 is reserved for turning around the AD bus, so the target is not permitted to drive data on the bus even if it is capable of fast DEVSEL.
A target that supports fast DEVSEL could in theory begin responding to a read the cycle after the address is presented.
This cycle is, however, reserved for AD bus turnaround. Note that most targets will not be this fast and will not need any special logic to enforce this condition.
Either side may request that a burst end after the current data phase. Simple PCI devices that do not support multi-word bursts will always request this immediately.
Even devices that do support bursts will have some limit on the maximum length they can support, such as the end of their addressable memory.
The cycle after the target asserts TRDY , the final data transfer is complete, both sides deassert their respective RDY signals, and the bus is idle again.
Obviously, it is pointless to wait for TRDY in such a case. The target requests the initiator end a burst by asserting STOP.
The initiator will then end the transaction by deasserting FRAME at the next legal opportunity; if it wishes to transfer more data, it will continue in a separate transaction.
There are several ways for the target to do this:. There will always be at least one more cycle after a target-initiated disconnection, to allow the master to deassert FRAME.
There are two sub-cases, which take the same amount of time, but one requires an additional data phase:. If the initiator ends the burst at the same time as the target requests disconnection, there is no additional bus cycle.
For memory space accesses, the words in a burst may be accessed in several orders. The unnecessary low-order address bits AD[1: A target which does not support a particular order must terminate the burst after the first word.
Some of these orders depend on the cache line size, which is configurable on all PCI devices. If the starting offset within the cache line is zero, all of these modes reduce to the same order.
Cache line toggle and cache line wrap modes are two forms of critical-word-first cache line fetching. Toggle mode XORs the supplied address with an incrementing counter.
This is the native order for Intel and Pentium processors. It has the advantage that it is not necessary to know the cache line size to implement it.
When one cache line is completely fetched, fetching jumps to the starting offset in the next cache line. Note that most PCI devices only support a limited range of typical cache line sizes; if the cache line size is programmed to an unexpected value, they force single-word access.
This is rarely used, and may be buggy in some devices; they may not support it, but not properly force single-word access either. That might be their turnaround cycle.
As the initiator is also ready, a data transfer occurs. This repeats for three more cycles, but before the last one clock edge 5 , the master deasserts FRAME , indicating that this is the end.
On clock edge 7, another initiator can start a different transaction. This is also the turnaround cycle for the other control lines. The equivalent read burst takes one more cycle, because the target must wait 1 cycle for the AD bus to turn around before it may assert TRDY:.
On clock edge 6, the target indicates that it wants to stop with data , but the initiator is already holding IRDY low, so there is a fifth data phase clock edge 7 , during which no data is transferred.
The PCI bus detects parity errors, but does not attempt to correct them by retrying operations; it is purely a failure indication.
Due to this, there is no need to detect the parity error before it has happened, and the PCI bus actually detects it a few cycles later.
During a data phase, whichever device is driving the AD[ The device listening on the AD bus checks the received parity and asserts the PERR parity error line one cycle after that.
This generally generates a processor interrupt, and the processor can search the PCI bus for the device which detected the error.
The PERR line is only used during data phases, once a target has been selected. If a parity error is detected during an address phase or the data phase of a Special Cycle , the devices which observe it assert the SERR System error line.
Due to the need for a turnaround cycle between different devices driving PCI bus signals, in general it is necessary to have an idle cycle between PCI bus transactions.
Additional timing constraints may come from the need to turn around are the target control lines, particularly DEVSEL. The target deasserts DEVSEL , driving it high, in the cycle following the final data phase, which in the case of back-to-back transactions is the first cycle of the address phase.
One case where this problem cannot arise is if the initiator knows somehow presumably because the addresses share sufficient high-order bits that the second transfer is addressed to the same target as the previous one.
In that case, it may perform back-to-back transactions. All PCI targets must support this. It is also possible for the target keeps track of the requirements.
Targets which have this capability indicate it by a special bit in a PCI configuration register, and if all targets on a bus have it, all initiators may use back-to-back transfers freely.
A subtractive decoding bus bridge must know to expect this extra delay in the event of back-to-back cycles in order to advertise back-to-back support.
Starting from revision 2. This is provided via an extended connector which provides the bit bus extensions AD[ The bit PCI connector can be distinguished from a bit connector by the additional bit segment.
During a bit burst, burst addressing works just as in a bit transfer, but the address is incremented twice per data phase.
The starting address must be bit aligned; i. AD2 must be 0. Note that a target may decide on a per-transaction basis whether to allow a bit transfer.
If REQ64 is asserted during the address phase, the initiator also drives the high 32 bits of the address and a copy of the bus command on the high half of the bus.
If the address requires 64 bits, a dual address cycle is still required, but the high half of the bus carries the upper half of the address and the final command code during both address phase cycles; this allows a bit target to see the entire address and begin responding earlier.
The data which would have been transferred on the upper half of the bus during the first data phase is instead transferred during the second data phase.
If ACK64 is missing, it may cease driving the upper half of the data bus. It is only valid for address phases if REQ64 is asserted. PCI originally included optional support for write-back cache coherence.
Because this was rarely implemented in practice, it was deleted from revision 2. In the case of a write to data that was clean in the cache, the cache would only have to invalidate its copy, and would assert SDONE as soon as this was established.
However, if the cache contained dirty data, the cache would have to write it back before the access could proceed. In the meantime, the cache would arbitrate for the bus and write its data back to memory.
Targets supporting cache coherency are also required to terminate bursts before they cross cache lines. Logic analyzers and bus analyzers are tools which collect, analyze, and decode signals for users to view in useful ways.
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NET by Eric Seppanen. Retrieved July 13, The ZX Series is a true bit adapter, widening the network pipeline to achieve higher throughput, while offering backward compatibility with standard bit PCI slots.
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